Physical JTAG compliant component
Back in 1985 in response to the increasing density of then new electronics packaging technologies, test engineers from the major silicon vendors in Europe formed the Joint European Test Action Group
and set about forming proposals for a new way of testing electronic devices mounted on a printed circuit board. In 1986 the group expanded to include members from North America and was renamed
the Joint Test Action Group. The findings and recommendations of this group were used as the basis for the Institute of Electrical and Electronic Engineers (IEEE) standard 1149.1: Standard Test Access
Port and Boundary Scan Architecture. This standard is commonly know by the acronym JTAG, derived from the name of the group that formulated it.
The initial purpose of the JTAG standard, also referred to as Boundary Scan, was to set out a system that could be built into an IC to allow testing of the physical connection of the pins of the chip without
the need to connect probes to the pins. It was conceived as an alternative or replacement for traditional bed-of-nails testing, which can be difficult or impossible on many modern high-density surface mount boards. On a JTAG compliant device, each physical pin of the device is connected to the underlying logic via a small piece of circuitry called a Boundary Scan cell. Each cell is configured to be able to monitor the value of the device pin, and each cell is connected to its adjacent cells to form a serial chain allowing data to be extracted from the Boundary Scan cells without having to connect to each individual pin.
The full JTAG implementation requires only four pins on a device – TDI to load serial data in, TDO to extract serial data out, the TMS control line and the TCK JTAG clock, as shown in Figur. The Test Access Port
The heart of JTAG communications is the Test Access Port or TAP. The TAP defines a set of registers and a controller that are used to define the operation of the JTAG interface. There are two types of registers associated with boundary scan. Each compliant device has one instruction register and two or more data registers. The instruction register holds the current instruction. Its content is used by the TAP controller to decide what to do with signals that are received. Most commonly, the content of the instruction register will
define which of the data registers signals should be passed to. There are three primary data registers:
1. Boundary Scan Register (BSR) – this is the main testing data register and is formed by the JTAG cells connected between the core logic and the pins of the device. It is used to move data to and from the ‘pins’ on a device.
2. BYPASS – this is a single-bit register that passes information from TDI to TDO. It allows other devices in a circuit to be tested with minimal overhead.
3. IDCODES – this register contains the ID code and revision number for the device. This information allows the device to be linked to its Boundary Scan Description Language (BSDL) file. The file contains details of the Boundary Scan configuration for the device.
Other data registers may be present, but they are not required as part of the JTAG standard.
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