While the JTAG standard was originally designed to allow physical testing of devices during PCB
assembly, it has been adapted for a variety of uses, most notably to provide in-circuit programmability
to FPGAs.
Another use of JTAG has been to provide communications for the implementation of on-chip
debugging functions in microprocessors. To this end a group known as the Nexus 5001 Forum
(formerly the Global Embedded Processor Debug Interface Consortium) have developed IEEE/ISTO
5001: Standard for a Global Embedded Processor Debug Interface. This standard, which we will refer to as the Nexus standard, leverages the pin interface established by the JTAG standard and adds
specific protocols and API features designed to address processor debugging needs.
A complete description of the Nexus standard is beyond the scope of this article. You can download
the full standard from the Nexus 5001 Forum web site at www .nexus5001.org.
Nexus components
The platform makes use of the Nexus standard by using it as the basis for communications with the
‘soft’ processor cores and virtual instruments used within the system. These devices, which are
provided in pre-synthesized form ready for implementation inside an FPGA, include a JTAG port and
use features of the Nexus standard to enable On Chip Debug or Instrument Control layers within the
device, as shown in Figure.
Nexus components
The advantage of using the JTAG and Nexus standards in the implementation of FPGA-based devices
is that these devices can be chained together and accessed from the design environment with little pin
overhead on the FPGA. Also, devices can be chained through multiple FPGAs, allowing a complete
view of all controllable devices in a larger, multiple FPGA-based system.
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