Interrupt Controller
The Interrupt ReQuests (IRQ’s) of a PC is handled by two 8259 Programmable Interrupt Controllers. On the old XT’s/AT’s these were two 28 Pin DIP IC’s, but as you can imagine, things have changed dramatically since then. While the operational principal is still the same, the PIC is now integrated somewhere into your chipset, along with many other devices. As we have all ready discussed, the Interrupt ReQuests (IRQ’s) of a PC is handled by two 8259 Programmable Interrupt Controllers. On the old XT’s/AT’s these were two 28 Pin DIP IC’s, but as youcan imagine, things have changed dramatically since then. While the operational principal is still thesame, the PIC is now integrated somewhere into your chipset, along with many other devices.
The basic block diagram of the PIC is shown above. The 8 individual interrupt request lines are first passed through the Interrupt Mask Register (IMR) to see if they have been masked or not. If they are masked, then the request isn’t processed any further. However if they are not masked, they will register their request with the Interrupt Request Register (IRR). The Interrupt Request Register will hold all the requested IRQ’s until they have been dealt with appropriately. If required, this register can be read by setting certain bits of the Operation Control Word 3. The Priority Resolver simply selects the IRQ of highest priority. The higher priority interrupts are the lower numbered ones.
For Example IRQ 0 has the highest priority followed by IRQ 1 etc. Now that the PIC has determined which IRQ to process, it is now time to tell the processor, so that it can call your ISR for you. This process is done by sending a INT to the processor, i.e. the INT line on the processor is asserted. The processor will then finish the current instruction it’s processing and acknowledge your INT request with a INTA (Interrupt Acknowledge) pulse. Upon receiving the processor’s INTA, the IRQ which the PIC is processing at the time is stored in the In Service Register (ISR) which as the name suggests, shows which IRQ is currently in service. The IRQ’s bit is also reset in the Interrupt Request Register, as it is no longer requesting service but actually getting service. Another INTA pulse will be sent by the processor, to tell the PIC to place a 8 bit pointer on the data bus, corresponding to the IRQ number. If an IRQ serviced by PIC2 is requesting the service, then PIC2 will send the pointer to the processor. The Master (PIC1) at this stage, will select PIC2 to send the pointer, by placing PIC2′s Slave ID on the Cascade lines, which is a 3 wire bus between all the PIC’s in a system. The 5 most significant bits of this pointer is set using the Initialization Command Word 2 (ICW2). This will be 00001 for PIC1 and 01110 for PIC2. The three least significant bits, will be sent due to which IRQ is being serviced. For example, if IRQ3 is requesting service then the 8 bit pointer will be made up with 00001 for the 5 most significant bits and 011 (IR3) for the least significant bits. Put this together and you get 00001011 or 0x0B which just happens to be IRQ3′s interrupt vector.
For PIC2, the same principal is applied. If IRQ10 is requesting service, then 01110010 will be sent, which just happens to represent Interrupt 72h. IRQ10 happens to be connected to IR2 on the Second PIC, thus 010 is used as the least significant bits.
Once your ISR has done everything it needs, it sends an End of Interrupt (EOI) to the PIC, which resets the In-Service Register. If the request came from PIC2, then EOI’s are required to be sent to both PICs. The PIC will then determine the next highest priority interrupt and repeat the same process. If no Interrupt Requests are present, then the PIC waits for the next request before interrupting the processor.
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