image proccessing sensor

• Micron DigitalClarityTM CMOS imaging technology
• Array Format (5:4): 1,280H x 1,024V (1,310,720 active
pixels). Total (incl. dark pixels): 1,312H x 1,048V
(1,374,976 pixels)
• Frame Rate: 30 fps progressive scan; programmable
• Shutter: Electronic Rolling Shutter (ERS)
• Window Size: SXGA; programmable to any smaller
format (VGA, QVGA, CIF, QCIF, etc.)
• Programmable Controls: Gain, frame rate, frame size

The Micron Imaging MT9M001 is an SXGA-format with a 1/2-inch CMOS active-pixel digital image sensor. The active imaging pixel array of 1,280H x 1,024V. It incorporates sophisticated camera functions on-chip such as windowing, column and row skip mode, and snapshot mode. It is programmable through a simple two-wire serial interface.

This megapixel CMOS image sensor features Digital Clarity—Micron’s breakthrough low-noise CMOS imaging technology that achieves CCD image quality (based on signal-to-noise ratio and low-light sensitivity) while maintaining the inherent size, cost, and integration advantages of CMOS. The sensor can be operated in its default mode or programmed by the user for frame size, exposure, gain setting, and other parameters. The default mode outputs an SXGA-size image at 30 frames per second (fps). An on-chip analog-to-digital converter (ADC) provides 10 bits per pixel. FRAME_VALID and LINE_VALID signals are output on dedicated pins, along with a pixel clock that is synchronous with valid data.

Serial Bus Description
Registers are written to and read from the MT9M001 through the two-wire serial inter-face bus. The sensor is a two-wire serial interface slave and is controlled by the serial clock (SCLK), which is driven by the serial interface master. Data is transferred into and of the MT9M001 through the serial data (SDATA) line. The SDATA line is pulled up to 3.3V off-chip by a 1.5K? resistor. Either the slave or master device can pull the SDATA line down—the serial interface protocol determines which device is allowed to pull the SDATA line down at any given time.

Sequence
A typical read or write sequence begins by the master sending a start bit. After the start bit, the master sends the slave device’s eight-bit address. The last bit of the address termines if the request will be a read or a write, where a “0” indicates a write and a “1” indicates a read. The slave device acknowledges its address by sending an acknowledge bit back to the master. If the request was a write, the master then transfers the 8-bit register address to which a write should take place. The slave sends an acknowledge bit to indicate that the register address has been received. The master then transfers the data eight bits at a time, with the slave sending an acknowledge bit after each eight bits. The MT9M001 uses 16-bit data for its internal registers, thus requiring two 8-bit transfers to write to one register. After 16 bits are transferred, the register address is automatically incremented, so that the next 16 bits are written to the next register address. The master stops writing by sending a start or stop bit.
A typical read sequence is executed as follows. First the master sends the write-mode slave address and 8-bit register address, just as in the write request. The master then sends a start bit and the read-mode slave address. The master then clocks out the register data eight bits at a time. The master sends an acknowledge bit after each 8-bit
transfer. The register address is auto-incremented after every 16 bits is transferred. The data transfer is stopped when the master sends a no-acknowledge bit.

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