The serial USART provide for full duplex (two-way) communication between a receiver and
transmitter. This is accomplished by equipping the ATmega16 with independent hardware for the
transmitter and receiver. The USART is typically used for asynchronous communication. That is,
there is not a common clock between the transmitter and receiver to keep them synchronized with
one another. To maintain synchronization between the transmitter and receiver, framing start and
stop bits are used at the beginning and end of each data byte in a transmission sequence. The
Atmel USART also has synchronous features. Space does not permit a discussion of these USART
enhancements.
The ATmega16 USART is quite flexible. It has the capability to be set to a variety of data
transmissionor baud (bits per second) rates.The USART may also be set for data bit widths of 5 to 9
bits with one or two stop bits. Furthermore, the ATmega16 is equipped with a hardware-generated
parity bit (even or odd) and parity check hardware at the receiver. A single parity bit allows for
the detection of a single bit error within a byte of data. The USART may also be configured to
operate in a synchronous mode. We now discuss the operation, programming, and application of
the USART. Because of space limitations, we cover only the most basic capability of this flexible
and powerful serial communication system.
System Overview
The block diagram for the USART is provided in Figure 2.2. The block diagram may appear a
bit overwhelming, but realize there are four basic pieces to the diagram: the clock generator, the
Atmel AVR ATmega16 USART block diagram. Figure used with permission of Atmel
transmission hardware, the receiver hardware, and three control registers (UCSRA, UCSBR, and
UCSRC).We discuss each in turn.
1. USART ClockGenerator
The USART Clock Generator provides the clock source for
the USART system and sets the baud rate for the USART. The baud rate is derived from the
overall microcontroller clock source. The overall system clock is divided by the USART baud rate
registers UBRR[H:L] and several additional dividers to set the baud rate. For the asynchronous
normal mode (U2X bit = 0), the baud rate is determined using the following expression:
baud rate=(system clock frequency)/(2(UBRR + 1)),
where UBRR is the content of the UBRRH and UBRRL registers (0–4095). Solving for UBRR
yields
UBRR=((system clock generator)/(16 × baud rate))- 1
2. USART Transmitter
The USART transmitter consists of a Transmit Shift Register.
The data to be transmitted are loaded into the Transmit Shift Register via the USART I/O Data
Register (UDR). The start and stop framing bits are automatically appended to the data within the
Transmit Shift Register. The parity is automatically calculated and appended to the Transmit Shift
Register. Data are then shifted out of the Transmit Shift Register via the TxD pin a single bit at
a time at the established baud rate. The USART transmitter is equipped with two status flags: the
USART Data Register Empty (UDRE) and the transmit complete (TXC) flags. The UDRE flag
sets when the transmit buffer is empty, indicating it is ready to receive new data. This bit should be
written to a zero when writing the USART Control and Status Register A (UCSRA). The UDRE
bit is cleared by writing to the UDR. The TXC flag bit is set to logic 1 when the entire frame in
the Transmit Shift Register has been shifted out and there are no new data currently present in the
transmit buffer. The TXC bit may be reset by writing a logic 1 to it.
3. USARTReceiver.
TheUSART Receiver is virtually identical to theUSART Transmitter
except for the direction of the data flow, which is reversed. Data are received a single bit at a time
via the RxD pin at the established baud rate. The USART receiver is equipped with the receive
complete (RXC) flag. The RXC flag is logic 1 when unread data exist in the receive buffer.
4. USART Registers.
In this section, we discuss the register settings for controlling the
USART system. We have already discussed the function of the UDR and the USART baud rate
registers (UBRRH and UBRRL). Note: The USART Control and Status Register C (UCSRC)
and the USART baud rate register high (UBRRH) are assigned to the same I/O location in the
memory map (Figure 2.3). The URSEL bit (bit 7 of both registers) determines which register
USART registers
is being accessed. The URSEL bit must be 1 when writing to the UCSRC register and 0 when
writing to the UBRRH register.
UCSRA. This contains the RXC, TXC, and the UDRE bits. The function of these bits has
already been discussed.
UCSRB. This contains the receiver and transmitter enable bits (RXEN and TXEN,
respectively). These bits are the ‘‘on/off’’ switch for the receiver and transmitter, respectively. The
UCSRB register also contains the UCSZ2 bit. The UCSZ2 bit in the UCSRB register and the
UCSZ[1:0] bits contained in the UCSRC register together set the data character size UCSRC. This allows the user to customize the data features to the application at hand. It
should be emphasized that both the transmitter and receiver be configured with the same data
features for proper data transmission. The UCSRC contains the following bits:
• USART mode select (UMSEL): 0, asynchronous operation; 1, synchronous operation
• USART parity mode (UPM[1:0]): 00, no parity; 10, even parity; 11, odd parity
• USART stop bit select (USBS): 0, one stop bit; 1, two stop bits
• USART character size (data width) (UCSZ[2:0]): 000, 5 bits; 001, 6 bits; 010; 7 bits; 011,
8 bits; 111, 9 bits
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