The ATmega16 SPI also provides for two-way serial communication between a transmitter and
a receiver. In the SPI system, the transmitter and receiver share a common clock source. This
requires an additional clock line between the transmitter and receiver but allows for higher data
transmission rates as compared with the USART. The SPI system allows for fast and efficient data
exchange between microcontrollers or peripheral devices. There are many SPI-compatible external
systems available to extend the features of the microcontroller. For example, a liquid crystal display
(LCD) or a digital-to-analog converter (DAC) could be added to the microcontroller using the
SPI system.
SPI Operation.
TheSPImaybeviewedasasynchronous16-bitshiftregisterwithan
8-bit half residing in the transmitter and the other 8-bit half residing in the receiver as shown in
Figure 2.5. The transmitter is designated the master because it provides the synchronizing clock
source between the transmitter and the receiver. The receiver is designated as the slave. A slave
is chosen for reception by taking its slave select (SS) line low. When the SS line is taken low,
the slave’s shifting capability is enabled. SPI transmission is initiated by loading a data byte into
the master configured SPI Data Register (SPDR). At that time, the SPI clock generator provides
clock pulses to the master and also to the slave via the SCK pin. A single bit is shifted out of the
master designated shift register on the Master Out Slave In (MOSI) microcontroller pin on every
SCK pulse. The data are received at the MOSI pin of the slave designated device. At the same
time, a single bit is shifted out of the Master In Slave Out (MISO) pin of the slave device and into
the MISO pin of the master device. After eight master SCK clock pulses, a byte of data has been
exchanged between the master and slave designated SPI devices. Completion of data transmission
in the master and data reception in the slave is signaled by the SPI Interrupt Flag (SPIF) in both
devices. The SPIF flag is located in the SPI Status Register (SPSR) of each device. At that time,
another data byte may be transmitted.
Registers.
The registers for the SPI system are provided in Figure 2.6. We will discuss
each one in turn.
SPI Control Register. The SPI Control Register (SPCR) contains the ‘‘on/off’’ switch for the
SPI system. It also provides the flexibility for the SPI to be connected to a wide variety of devices
with different data formats. It is important that both the SPI master and slave devices be configured
for compatible data formats for proper data transmission. The SPCR contains the following bits:
1. SPI Enable (SPE) is the ‘‘on/off’’ switch for the SPI system. A logic 1 turns the systemon
and logic 0 turns it off.
spi register
2.Data Order (DORD) allows the direction of shift from master to slave to be controlled.
When the DORD bit is set to 1, the least significant bit (LSB) of the SPDR is transmitted
first. When the DORD bit is set to 0, the Most Significant Bit (MSB) of the SPDR is
transmitted first.
3. The Master/Slave Select (MSTR) bit determines if the SPI system will serve as a master
(logic 1) or slave (logic 0).
4. The Clock Polarity (CPOL) bit allows determines the idle condition of the SCK pin.
When CPOL is 1, SCK will idle logic high, whereas when CPOL is 0, SCK will idle
logic 0.
5. TheClockPhase(CPHA)determinesifthedatabitwillbesampledontheleading(0)or
trailing (1) edge of the SCK.
6. The SPI SCK is derived from the microcontroller’s systemclock source. The systemclock
is divided down to formthe SPI SCK. The SPI Clock Rate Select (SPR[1:0]) bits and the
Double SPI Speed (SPI2X) bit are used to set the division factor. The following divisions
may be selected using SPI2X, SPR1, and SPR0:
{ 000: SCK = systemclock/4
{ 001: SCK = systemclock/16
{ 010: SCK = systemclock/64
{ 011: SCK = systemclock/1284
{ 100: SCK = systemclock/2
{ 101: SCK = systemclock/8
{ 110: SCK = systemclock/32
{ 111: SCK = systemclock/64
SPI Status Register. This contains the SPIF. The flag sets when eight data bits have been
transferred from the master to the slave. The SPIF bit is cleared by first reading the SPSR after the
SPIF flag has been set and then reading the SPDR. The SPSR also contains the SPI2X bit used to
set the SCK frequency.
SPI Data Register. As previously mentioned, writing a data byte to the SPDR initiates SPI
transmission.
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