In this section, we describe the overall architecture of the Atmel AVR ATmega16.We begin with an introduction to the concept of the reduced instruction set computer (RISC) and briefly describe the Atmel Assembly Language Instruction Set. A brief introduction is warranted because we will be programming mainly in C throughout the course of the book. We then provide a detailed description of the ATmega16 hardware architecture.
Reduced Instruction Set Computer
Microcontroller operation is controlled by a user-written program interacting with the fixed hardware architecture resident within the microcontroller. A specific microcontroller architecture can be categorized as accumulator-based, register-based, stack-based, or a pipeline architecture. The Atmel ATmega16 is a register-based architecture. In this type of architecture, both operands of an operation are stored in registers collocated with the central processing unit (CPU). This means that before an operation is performed, the computer loads all necessary data for the operation to its CPU. The result of the operation is also stored in a register. During program execution, the CPU interacts with the register set and minimizes slowermemory accesses.Memory accesses are typically handled as background operations.
Coupled with the register-based architecture is an instruction set based on the RISC concept.
A RISC processor is equipped with a complement of very simple and efficient basic operations. More complex instructions are built up from these very basic operations. This allows for efficient program operation. The Atmel ATmega16 is equipped with 131 RISC-type instructions. Most can be executed in a single clock cycle. The ATmega16 is also equipped with additional hardware to allow for the multiplication operation in two clock cycles. In many other microcontroller architectures, multiplication typically requires many more clock cycles. For additional information on the RISC architecture, the interested reader is referred to Hennessy and Patterson [3].
The Atmel ATmega16 [2] is equipped with 32 general purpose 8-bit registers that are tightly coupled to the processor’s arithmetic logic unit within the CPU. Also, the processor is designed following the HarvardArchitecture format.That is, it is equipped with separate, dedicated memories and buses for program and data information. The register-based Harvard Architecture coupled with the RISC-based instruction set allows for fast and efficient program execution and
allows the processor to complete an assembly language instruction every clock cycle. Atmel indicates the ATmega16 can execute 16 million instructions per second when operating at a clock speed of
16 MHz.
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