ARM7EJ-S processor block, core, and interface diagrams
Arm7 the i9 Phone Processor
About the ARM7EJ-S processor with Jazelle technology
The ARM7EJ-S processor has the ARMv5TEJ architecture with Jazelle technology featuring an enhanced multiplier design for improved Digital Signal Processing (DSP) performance.The Jazelle technology enables direct execution of Java bytecodes on ARM processors, providing the performance for the next generation of Java-powered
wireless and embedded devices. The ARM7EJ-S processor is a member of the ARM family of general-purpose 32-bit
microprocessors. The ARM family of processors offers high performance for very low power consumption and gate count.
The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles. The reduced instruction set and related decode mechanism are much simpler than those of Complex Instruction Set Computer (CISC) designs. This simplicity gives:
• a high instruction throughput
• an excellent real-time interrupt response
• a small, cost-effective, processor macrocell.
The instruction pipelines
The ARM7EJ-S processor uses a pipeline to increase the speed of the flow of instructions to the processor. This enables several operations to take place simultaneously, and the processing and memory systems to operate continuously.
A five-stage ARM state pipeline is used, consisting of Fetch, Decode, Execute, Memory, and Writeback stages. This is shown in Figure 1-1 on page 1-3. A six-stage pipeline is used in Jazelle state, consisting of Fetch, Jazelle, Decode,
Execute, Memory, and Writeback stages. This is shown in Figure 1-2 on page 1-4.
Five-stage pipeline
During normal operation:
• one instruction is being fetched from memory
• the previous instruction is being decoded
• the instruction before that is being executed
• the instruction before that is performing data accesses (if applicable)
• the instruction before that is writing its data back to the register bank.
Note
The program counter points to the instruction being fetched rather than to the instructionbeing executed.
Six-stage Jazelle pipeline
ARM7EJ-S processor architecture
The ARM7EJ-S processor has three instruction sets:
• the 32-bit ARM instruction set used in ARM state
• the 16-bit Thumb instruction set used in Thumb state
• the 8-bit Java bytecode used in Jazelle state.
The ARM7EJ-S processor uses the v5TEJ implementation of the ARM architecture. For details of both the ARM and Thumb instruction sets, refer to the ARM Architecture Reference Manual. For full details of the Jazelle instruction set, refer to
http://java.sun.com.
This section describes:
• Instruction compression
• The Thumb instruction set.
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