The MC74HC595A consists of an 8?bit shift register and an 8bit type latch with three state parallel outputs. The shift register accepts serial data and provides a serial output. The shift register also provides parallel data to the 8bit latch. The shift register and latch have independent clock inputs. This device also has an asynchronous
reset for the shift register.
The HC595A directly interfaces with the SPI serial data port on CMOS MPUs and MCUs.
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 A
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC
Standard No. 7A
• Chip Complexity: 328 FETs or 82 Equivalent Gates
• Improvements over HC595
Improved Propagation Delays
50% Lower Quiescent Power
Improved Input Noise and Latchup Immunity
• PbFree Packages are Available*
8 Bit Serial Input-Serial or Parallel Output Shift Register with Latched 3-State Outputs
Shift Register configuration
Keyword :
shift register ,shift registers ,flip-flop ,clock pulse ,bit shift ,universal shift register ,shifts ,ring counter ,positions ,parallel data ,outputs ,timing diagram ,symbol ,static shift register ,states ,serial input ,serial data ,sequential logic ,rising edge ,registers ,polynomial ,microprocessor ,latches ,johnson counter ,inputs and outputs ,values ,turn on ,the shift ,solenoid ,shift-left ,sensor input ,peanuts ,parallel load ,one bit ,ladder ,instruction ,inputs ,ice-cream cone ,ice cream ,galois ,flip-flops ,encoder ,downto ,datasheet ,data input ,conveying system ,configuration ,computer science ,clock pulses ,circuits ,circuit ,choo-choo train ,bit serial ,bit parallel ,bidirectional ,asynchronous ,-state.
